Riverlane’s

Riverlane, a Cambridge company founded in 2016, builds Deltaflow, a real-time system that catches and corrects errors inside quantum computers as they run, plus Deltakit, free open-source software for learning and testing error correction.

Riverlane at a glance

Every quantum computer makes errors, and a useful one will need to correct them faster than they pile up. That is Riverlane's whole focus. Based in Cambridge , UK, with further offices in Boston and Delft, it builds Deltaflow, a real-time quantum error correction system designed to work as a hardware-agnostic layer on top of any type of qubit.

Riverlane says it partners with over 60% of the world's quantum computer companies.

Deltaflow 3, which adds streaming logic, was planned for 2026. A MegaQuOp target for 2026 came from the July 2024 roadmap; Riverlane's March 2026 roadmap moved it out. Deltaflow Mega, for fully error-corrected applications, is further out: Riverlane's roadmap expects MegaQuOp systems, able to run a million error-free operations, before the end of the decade.

In April 2026 Riverlane reported a 16.32 microsecond mean decoding latency for Deltaflow 2, against the 63 microseconds Google published; that comparison replayed Google's 2024 Willow dataset through Riverlane's own emulator rather than running on a live machine. If you want to try error correction yourself, Deltakit is Riverlane's free, open-source Python toolkit for building, simulating and decoding error-correction experiments, no quantum computer required.

On 4 September 2025 Riverlane announced that Oak Ridge National Laboratory would install Deltaflow 2, integrated with the lab's OLCF HPC ecosystem ( of Frontier), with installation scheduled to finish by the end of September 2025. Connecting it to quantum hardware was planned as a later phase.

In July 2025 Riverlane integrated Deltaflow 2 at a CentreSquare data centre co-located with OQC's quantum computer, with Qblox control hardware, under the UK DECIDE project. Real-time QEC on live OQC qubits was planned, not yet done. Work with Infleqtion and Rigetti runs through separate NQCC-supported collaborations.

In December 2025 it opened its Delft hub, led by Riverlane Fellow Professor Barbara Terhal, and in September 2026 it announced a US headquarters in Maryland, near the University of Maryland , building on its presence in Boston.

In August 2024 Riverlane raised a $75M Series C led by Planet First Partners , with ETF Partners, EDBI, Cambridge Innovation Capital , Amadeus Capital Partners , the UK National Security Strategic Investment Fund and Altair. It had put its total funding at 55 million pounds in May 2024, before that round closed; its own materials now describe an $85 million Series C and more than $120 million raised in private funding.

Steve Brierley, a former senior research fellow at the University of Cambridge , founded Riverlane in 2016 and leads it as chief executive.

The company now has more than 180 people, and its Fellows include Barbara Terhal, Earl Campbell and Dan Browne.

Riverlane has chosen the Discovery District in Maryland as its U.S. headquarters. quantumzeitgeist.com

Riverlane opened its US headquarters in the Discovery District in College Park, Maryland. quantumzeitgeist.com

Altera and Riverlane have validated Riverlane’s Quantum Error Correction Interface (QECi) on Altera Agilex 7 FPGAs, offering developers a platform for evaluating quantum error correction data movement and integration. quantumzeitgeist.com

Riverlane demonstrated quantum error correction tools, including Deltaflow and Deltakit, at IEEE Quantum Week. quantumzeitgeist.com

Riverlane launched the Deltakit Community Fund with the Unitary Foundation , awarding 2,000 to 4,000 dollars per feature for open-source quantum error correction work on its Deltakit toolkit. Named targets are error budgeting bounds, threshold computation and a ZX graph benchmark library. Riverlane keeps technical oversight, defining criteria and reviewing milestones for adoption into the main package; the Unitary Foundation sets the merit framework. Structured as a quarterly initiative with two developer projects starting in the second half of 2026, open globally except where US export controls or sanctions apply. quantumzeitgeist.com

Riverlane and Rigetti's real-time decoding paper was published in Nature Communications: a 9.6 microsecond decoding response time in an 8-qubit stability experiment. nature.com

Riverlane reported a 16.32 microsecond mean decoding latency for Deltaflow 2, against the 63 microseconds Google published, with maximum sub-shot latency more than 10 times better. The run replayed Google's 2024 Willow dataset through Riverlane's own emulator rather than a live QPU. The live article says 16.32 microseconds and does not mention Rigetti; the earlier figure is not supported by any source. quantumzeitgeist.com

Riverlane and Qblox integrated Deltaflow 2 with Qblox control hardware, with a stated joint capacity of 250 physical qubits and 1 logical qubit. That is a capacity figure, not a demonstration. qblox.com

Riverlane published a roadmap detailing how its quantum error correction technology can potentially accelerate the development of utility-scale quantum computing by three to five years. quantumzeitgeist.com

Riverlane established a new European research and development hub in Delft, Netherlands, focused on advancing quantum error correction. quantumzeitgeist.com

Riverlane will install its Deltaflow 2 real-time quantum error correction system at Oak Ridge National Laboratory by the end of September 2025. quantumzeitgeist.com

Riverlane published the Quantum Error Correction Report 2024 with Resonance. The report says 66% of the 29 hardware companies it profiles are implementing or focused on QEC. A 2025 edition followed. web.archive.org

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Quantum Error Correction

Quantum error correction companies build codes and decoders to shield qubits from noise, covering surface codes, color codes, and bosonic approaches on...

Quantum software companies develop programming frameworks, compilers, simulators, and application layers that enable users to write and execute...

Riverlane quantum hardware

Deltaflow Mega - 1 million QuOps. Riverlane's Mar 2026 roadmap places this before the end of the decade, not in 2026.

Local Clustering Decoder published in Nature Communications, presented as the first hardware decoder for real-time scalable quantum error correction. FPGA-based and hardware-agnostic. Its reported 4x qubit saving comes from simulation under a leakage-dominated noise model, and "first" is Riverlane's own description.

Nature Electronics paper (7 January 2025) on the Collision Clustering decoder, implemented on FPGA and ASIC and benchmarked on simulated surface-code memory experiments (881 qubits on FPGA, 1,057 on ASIC). The decoder was not run on a quantum computer in this paper.

nature.com peer reviewed

Deltaflow 3 - streaming logic. No shipping announcement found as of Aug 2026.

9.6 microsecond decode-and-feedback response time over 9 measurement rounds, using an FPGA decoder on a Rigetti superconducting QPU. Peer reviewed in Nature Communications, published 1 June 2026 (DOI 10.1038/s41467-026-73331-6): an 8-qubit stability experiment reporting logical error suppression as rounds increase, not a below-threshold memory.

nature.com peer reviewed

Deltaflow 2 performs real-time error correction on up to 250 physical qubits using the Local Clustering Decoder (Riverlane product specification). This is a capacity figure, not a demonstration.

web.archive.org official

Ambiguity Clustering decoder - 27x speedup for qLDPC codes

Source:

Riverlane software and frameworks

A robust, open-source physical layer implementation for FPGA-to-FPGA communication over high-speed serial links of the Quantum Error Correction interface (QECi) PHY layer.

Riverlane's free, open-source Python toolkit for designing, simulating and decoding quantum error correction experiments, with a free token for its cloud-hosted decoder.

purification-without-post-selection

Source code used to generate the data in "Post-selection-free preparation of high-quality physical qubits" by Ben Barber, Neil I. Gillespie and J. M. Taylor.

Hardware and Services

The second generation of Deltaflow: an FPGA-based QEC system combining Riverlane's hardware decoder with high-throughput data routing, connected directly to the quantum control stack. It was first delivered to Rigetti and integrated with Infleqtion's Sqale system in early 2025, and Oak Ridge National Laboratory announced it would install it in September 2025.

Riverlane's real-time quantum error correction system, built on FPGA hardware, which sits as a layer in the quantum computing stack and decodes errors across logical qubits as the machine runs. The company says it works with all major qubit types and includes its own QEC chips, decoders and a compiler.

The Quantum Error Correction interface, a specification Riverlane is developing for how a quantum computer's control system talks to its QEC stack, defining data format, runtime states and parameters. Anyone can download and adopt the specification.

Riverlane error correction

Codes and published results, each read against its paper or announcement. A code that only detects errors, or a result kept by discarding runs, is labelled as such. All QEC results

Bivariate bicycle codes, including the 144-qubit gross code · Software support, 2024

Real-time decoding for qLDPC codes (Deltaflow Mega, 2024 roadmap target) · Stated path

Surface code (rotated) · Software support, 2023

Surface-code stability experiment (8 qubits) decoded in real time on a Rigetti superconducting processor · Demonstrated, 2024

Lattice surgery on surface-code logical qubits (SurgeonQ project with IQM and Zurich Instruments, target) · Stated path, 2025

Sep 2026 Full real-time QEC loop with Qblox control hardware over QECi, using emulated qubit measurement data Surface code (Surface-17 to Surface-161) · round-trip latency 6.886 us at distance 3 (Surface-17) to 11.886 us at distance 9 (Surface-161) Company claim Control and decoding hardware loop closed on emulated measurement data; no qubits. Company claim (Qblox newsroom, 11 September 2026). Source

Control and decoding hardware loop closed on emulated measurement data; no qubits. Company claim (Qblox newsroom, 11 September 2026).

Apr 2026 Deltaflow 2 latency measured on replayed Google Willow distance-5 surface-code memory data (emulated control system, no live qubits) Surface code (rotated) · 16.32 us mean latency (standard deviation 8.28 us) versus the 63 us Google reported; Riverlane says the comparison is not strictly like-for-like Company claim Decoder latency measured on replayed Google Willow distance-5 data through an emulated control system; no live qubits and no Riverlane logical qubit. Riverlane says the comparison with Google's 63 us is not strictly like-for-like. Source

Decoder latency measured on replayed Google Willow distance-5 data through an emulated control system; no live qubits and no Riverlane logical qubit. Riverlane says the comparison with Google's 63 us is not strictly like-for-like.

Dec 2025 · Nature Communications 16, 11048 (2025) Local Clustering Decoder: adaptive FPGA surface-code decoder, accuracy shown in simulation with a leakage-dominated noise model Surface code · one million error-free operations with 4x fewer physical qubits than standard non-adaptive decoding (simulated); under 1 us per decoding round on FPGA Peer reviewed Simulation for the 4x qubit saving (leakage-dominated circuit noise model); FPGA timing under 1 us per round is measured on the decoder hardware, not with qubits. Local clustering decoder as a fast and adaptive hardware decoder for the surface code

Simulation for the 4x qubit saving (leakage-dominated circuit noise model); FPGA timing under 1 us per round is measured on the decoder hardware, not with qubits.

Jan 2025 · Nature Electronics Collision Clustering decoder on FPGA and ASIC, benchmarked on simulated surface-code memory data (no qubits) Surface code · MHz decoding up to an 881-qubit surface code on FPGA and a 1,057-qubit surface code on ASIC; ASIC 0.06 mm2 and 8 mW Peer reviewed Simulation: decoder benchmarked on simulated surface-code memory data on FPGA and ASIC; no qubits. arXiv version title: 'A real-time, scalable, fast and highly resource efficient decoder for a quantum computer'. A real-time, scalable, fast and resource-efficient decoder for a quantum computer

Simulation: decoder benchmarked on simulated surface-code memory data on FPGA and ASIC; no qubits. arXiv version title: 'A real-time, scalable, fast and highly resource efficient decoder for a quantum computer'.

Oct 2024 · Nature Communications (published 1 June 2026) Real-time, low-latency FPGA decoding with fast feedback on a Rigetti superconducting processor Surface-code stability experiment from 8 physical · decoding response time of 9.6 us for 9 measurement rounds; mean decoding time per round below 1 us over up to 25 rounds Error-corrected Peer reviewed Hardware: 8-qubit surface-code stability experiment on a Rigetti processor, FPGA decoder in the control loop, up to 25 rounds, logical error suppression as rounds increase. A stability experiment, not a logical memory and not a below-threshold result. Joint Riverlane and Rigetti. Demonstrating real-time and low-latency quantum error correction with superconducting qubits

Hardware: 8-qubit surface-code stability experiment on a Rigetti processor, FPGA decoder in the control loop, up to 25 rounds, logical error suppression as rounds increase. A stability experiment, not a logical memory and not a below-threshold result. Joint Riverlane and Rigetti.

Jun 2024 Ambiguity Clustering decoder for qLDPC codes, benchmarked in simulation Bivariate bicycle codes (gross code) · up to 27x faster than BP-OSD with matched accuracy at 0.3% circuit-level noise; gross code decoded in 135us per round on an M2 CPU Preprint Simulation: circuit-level noise benchmark plus CPU timing; no qubits. Ambiguity Clustering: an accurate and efficient decoder for qLDPC codes

Simulation: circuit-level noise benchmark plus CPU timing; no qubits.

Riverlane partnerships and collaborations

14 known partnerships

IQM, Riverlane, and Zurich Instruments launched the SurgeonQ project, the world's first QEC platform combining Deltaflow with IQM's 20-qubit superconducting processor for real-time lattice-surgery error correction

Riverlane demonstrated the world's first low-latency real-time QEC experiment, integrating its scalable FPGA decoder into Rigetti's superconducting QPU control system; Deltaflow 2 subsequently deployed on Rigetti hardware

Riverlane deployed Deltaflow 2 at a commercial data centre co-located with OQC's quantum computer, first UK commercial QEC integration, pairing Riverlane's QEC stack with Qblox control hardware and OQC QPU

Riverlane participated in the Innovate UK £7.5M QEC consortium led by Universal Quantum with Rolls-Royce as end-user, targeting error-corrected quantum computing for aerospace simulation

Three-way SurgeonQ collaboration: Zurich Instruments supplied its Quantum Computing Control System for real-time communication between the quantum processor and Riverlane's Deltaflow QEC stack

Strategic collaboration to deliver integrated real-time QEC solution pairing Riverlane's Deltaflow decoders with Qblox's high-performance control hardware; jointly deployed at OQC commercial data centre

Fellow consortium member in the Innovate UK £7.5M grant to build a scalable, error-corrected quantum computer for aerospace applications

Deltaflow 2 deployed at ORNL, first dedicated real-time QEC at a US national lab

Part of Diraq's DARPA QBI Stage B consortium for silicon spin qubit error correction

Partner in quantum-classical integration via CUDA-Q framework

QEC research collaboration and Deltaflow integration with Google quantum hardware

Riverlane has partnered with Atlantic Quantum to advance quantum error correction technology.

Altera and Riverlane partnered to validate Riverlane’s QECi interface on Altera Agilex 7 FPGAs for quantum error correction systems.

Riverlane is collaborating with Infleqtion to advance quantum error correction in the UK by integrating its real-time technology with Infleqtion's neutral atom platform.

Named as a partner by

12 organisations record a partnership with Riverlane that this profile does not list.

What Riverlane has delivered, and what it has said is .

2026 Hardware decoder for fault-tolerant QEC unveiled achieved Cuts QEC latency around 10x faster than published Google results.

Cuts QEC latency around 10x faster than published Google results.

2025 Deltaflow 2 deployed at Oak Ridge National Laboratory achieved Hardware-agnostic QEC layer integrated with HPC infrastructure.

Hardware-agnostic QEC layer integrated with HPC infrastructure.

2024 First QEC chip implementation (Nature Electronics) achieved Demonstrated a real-time hardware decoder for quantum error correction.

Demonstrated a real-time hardware decoder for quantum error correction.

Riverlane founders and leadership

joined 2022 as Head of Architecture, later Riverlane Fellow

Riverlane Fellow, Delft

Riverlane company registration

From Companies House, the UK company register, checked 2026-09-05. Matched because the registered name equals the recorded name and the registered office town matches.

Amelia Sarah Armour · director, appointed 2019-04-23

Stephen Brierley · director, appointed 2016-07-04

Stuart Malcolm Chapman · director, appointed 2021-01-27

Andreas Hansson · director, appointed 2025-05-06

Nathan Alexander Medlock · director, appointed 2024-07-26

Andrew James Williamson · director, appointed 2019-04-23

Riverlane funding and investors

$125M total ($75M Series C 2024, led by Planet First Partners)

Investors that list Riverlane in their portfolio: Amadeus Capital Partners , Cambridge Innovation Capital , Molten Ventures , Planet First Partners , National Security Strategic Investment Fund , UK Research and Innovation (UKRI) .

$75M to meet demand for quantum error correction technology.

Latest Riverlane news

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Infleqtion and Riverlane team up on error correction for UK quantum computers

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Riverlane opens U.S. headquarters in Maryland for quantum work

Altera FPGAs now support Riverlane’s quantum error correction interface

Riverlane demos quantum error correction tools at IEEE event

Riverlane Funds Quantum Features for Open-Source Deltakit Toolkit

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Riverlane Cuts QEC Latency 10x Faster Than Google’s Results

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Riverlane Deploys Deltaflow 2 At Oak Ridge Lab

Riverlane Deploys Deltaflow 2 at Oak Ridge Lab to Demonstrate Real‑Time QEC

Riverlane Integrates QEC Tech at UK Commercial Quantum Data Centre

Riverlane Bolsters Quantum Error Correction Team with Key Industry Hires

Riverlane Joins DARPA’s Quantum Benchmarking Initiative with Key Role in Three Projects

IQM, Riverlane, and Zurich Instruments Unveil World’s First Quantum Error Correction Platform

Riverlane Appoints Liz Durst to Lead Quantum Error Correction Community

Riverlane advances quantum error correction with Deltaflow technology

Sheffield University Honors Quantum Error Correction Expert Earl Campbell VP Quantum Science At Riverlane

Pasqal Partners with Riverlane for Fault Tolerant Quantum Computing

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Can Riverlane's Deltaflow unlock useful quantum computing?

Is Riverlane’s Deltaflow the key to useful quantum computing?

Infleqtion and Riverlane team up on error correction for UK quantum computers

Infleqtion and Riverlane are collaborating to advance quantum error correction in the UK, integrating Riverlane’s real-time tech with Infleqtion’s neutral atom platform.

Maryland wins Riverlane’s U.S. headquarters, boosting quantum work

Riverlane chose Discovery District, Maryland for its U.S. headquarters, boosting the state’s growing quantum ecosystem.

Riverlane opens U.S. headquarters in Maryland for quantum work

Riverlane establishes its U.S. headquarters in Discovery District, Maryland, expanding its commitment to quantum error correction.

Altera FPGAs now support Riverlane’s quantum error correction interface

Altera and Riverlane partnered to help quantum hardware developers build flexible control and error-correction systems using Altera FPGAs, validating Riverlane’s QECi interface on Agilex 7 FPGAs. This enables low-latency…

Frequently asked questions Riverlane

Every quantum computer makes errors, and a useful one will need to correct them faster than they pile up. That is Riverlane's whole focus. Based in Cambridge, UK, with further offices in Boston and Delft, it builds Deltaflow, a real-time quantum error correction system designed to work as a hardware-agnostic layer on top of any type of qubit. Riverlane says it partners with over 60% of the world's quantum computer companies. Deltaflow 3, which adds streaming logic, was planned for 2026. A Me...

Riverlane is headquartered in Cambridge, United Kingdom.

Steve Brierley is the CEO of Riverlane.

Riverlane was founded by Steve Brierley in 2016.

Riverlane was founded in 2016.

Riverlane operates in the following sectors: quantum error correction, quantum software, quantum control.

Riverlane has raised $125M+ in total disclosed funding.

Investors that list Riverlane in their portfolio include Amadeus Capital Partners, Cambridge Innovation Capital, Molten Ventures, Planet First Partners, National Security Strategic Investment Fund and UK Research and Innovation (UKRI).

Companies working in the same areas as Riverlane include Error Corp, Commutator Studios, MagiQware, QC Design and QuantrolOx.